1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a shallow trench isolation (STI) layer of a semiconductor device for isolation of high-integration semiconductor device.
2. Discussion of the Related Art
With development in the technology for fabricating a semiconductor device and the increase of the applied field of semiconductor device, there is the active research and study for obtaining high integration of the semiconductor device. As the integration of the semiconductor device increases, various methods for obtaining the minuteness in the semiconductor device are developed and researched. On the technology for the minuteness of the semiconductor device, it is necessary to decrease a device isolation layer in width, thereby obtaining the high-integration semiconductor device.
For example, an LOCOS (LOCal Oxidation of Silicon) technology may be used to obtain the high-integration semiconductor device. In the LOCOS technology, a device isolation layer is formed by selectively growing a thick oxide layer on a semiconductor substrate. In this case, the oxide layer may be formed in the undesired portions, whereby it has the limitation on the decrease of the width of the device isolation layer. However, in case of the semiconductor device below submicron, it is impossible to apply the LOCOS technology.
Thus, an STI (Shallow Trench Isolation) technology is developed, wherein a shallow trench is formed in a semiconductor substrate by etching, and the shallow trench is buried with an insulating material. In case of the STI technology, it is possible to decrease a device isolation area.
Hereinafter, a method for fabricating an STI layer of a semiconductor device according to the related art will be described with reference to the accompanying drawings. FIG. 1A to FIG. 1G are cross sectional views of the process for fabricating an STI layer of a semiconductor device according to the related art.
As shown in FIG. 1A, a pad oxide layer SiO2 12 is formed on a silicon substrate 10 of a semiconductor substrate by the thermal oxidation process, wherein the pad oxide layer 12 functions as a buffer. At this time, the pad oxide layer 12 is formed at a thickness of 100 Å to 200 Å. Then, a silicon nitride layer Si3N4 14 is formed on the pad oxide layer 12 at a thickness of 1000 Å to 2000 Å, wherein the silicon nitride layer 14 functions as a hard mask layer.
Referring to FIG. 1B, a moat pattern 16 is formed on the hard mask layer 14, wherein the moat pattern 16 is provided to define an active area and a shallow trench isolation area in the semiconductor device. At this time, a photoresist is coated on the hard mask layer 14, and the exposure and development process is performed to the coated photoresist in state of using a mask pattern of an STI layer, thereby forming the moat pattern 16.
As shown in FIG. 1C, the hard mask layer 14 and the pad oxide layer 12 are patterned in the dry-etching process of using the moat pattern 16. In case of the dry-etching process of the hard mask layer 14, the hard mask layer 14 is dry-etched by plasma in the atmosphere of Ar gas with reaction gas of CHF3 and O2 inside an etching apparatus of an MERIE (Magnetically Enhanced Reactive Ion Etching) method. In this etching process, CHF3 gas is provided at 40 sccm to 80 sccm, O2 gas is provided at 0 sccm to 20 sccm, and Ar gas is provided 6 sccm to 120 sccm. Also, the etching apparatus of MERIE method is maintained at a pressure of 20 mTorr to 70 mTorr, and RF power is maintained at 200 W to 300 W.
As shown in FIG. 1D, the semiconductor substrate 10 exposed by the hard mask layer 14 and the pad oxide layer 12 is dry-etched at the predetermined depth, for example, about 3000 Å to 5000 Å. After forming a shallow trench 18 for fabrication of the STI layer, the moat pattern 16 is removed.
Although not shown, a linear insulating layer of silicon oxide SiO2 is thinly formed on the inner surface of the shallow trench 18, and the side of the pad oxide layer 12 and the hard mask layer 14.
Referring to FIG. 1E, a gap-fill insulating layer 20 of silicon oxide SiO2 or TEOS is formed to fill the shallow trench.
As shown in FIG. 1F, the gap-fill insulating layer 20 and the linear insulating layer are etched by CMP (Chemical Mechanical Polishing) until exposing the hard mask layer 14, thereby planarizing the surface of the gap-fill insulating layer 20 and the linear insulating layer. The reference number 20a indicates the gap-fill insulating layer after the planarization process.
In FIG. 1G, the hard mask layer 14 is removed with phosphoric acid. Then, the pad oxide layer 12 is partially removed by cleaning, thereby completing the STI layer 20a according to the related art.
In the process for fabricating the STI layer according to the related art, the STI layer of the insulating area is formed by performing the moat pattern formation and etching process after forming the pad oxide layer and the nitride layer.
However, the method for fabricating the semiconductor device according to the related art has the following disadvantages.
In the method for fabricating the semiconductor device according to the related art, it is impossible to obtain the STI layer critical dimension CD below the predetermined value due to the limitation of the related art. That is, the integration of the semiconductor device may be deteriorated since the area of the moat pattern for forming a gate line is decreased.